Roadmap¶

Six phases from Python interpreter to custom silicon.

Phase 1 — Python Interpreter¶

Status: 🟡 In Progress (~75% complete)

Build a fully functional Terse interpreter in Python. Validate the language design, syntax, and AI primitives. No native compilation yet — this phase is about getting the language right.

Milestone	Status
Lexer — tokenizes Terse source code	✅ Complete
Parser — builds AST from tokens	✅ Complete
Interpreter — executes AST, knowledge base, inference	✅ Complete
Markov chain sequence learning	✅ Complete
Functions — `to`/`return` syntax, scope	✅ Complete
Each loops	✅ Complete
`main.py` — run `.trs` files from command line	✅ Complete
First real `.trs` example program	✅ Complete
REPL — interactive Terse prompt	✅ Complete
While loops — wired into interpreter	🔵 Next
Error handling — line numbers in messages	🔵 Next
Tensors — native tensor type	⚪ Planned
Compression — `compress`/`expand` keywords	⚪ Planned
Ethics rules — `ethics`/`rule`/`deny`/`allow` syntax	⚪ Planned
Standard library — built-in functions in Terse	⚪ Planned

Phase 2 — C Transpiler¶

Status: ⚪ Planned

Terse code compiles to valid C, which is then compiled to native by GCC or Clang. First real performance. Same approach used by early C++ and Cython.

Code generator — walks AST and outputs C
Type mapping — Terse types to C types
Memory model — automated allocation and cleanup
Tensor output — maps to C arrays or BLAS
Build system — terse build command
Benchmark suite — compare Terse vs Python speed

Phase 3 — LLVM Compiler¶

Status: ⚪ Planned

Terse compiles directly to LLVM IR. Full optimization pipeline. Multi-architecture support. C-equivalent native speed on x86, ARM64, and RISC-V. Same backend used by Rust, Swift, and Clang.

Compilation targets:

Target	Architecture	Use Case
x86-64	Intel / AMD	Desktop and server
ARM64	Apple Silicon, CM5	Edge devices, NCI Box
RISC-V	Open silicon	Future NCI chip
NVPTX	NVIDIA GPU	Tensor acceleration
NCI-1	Custom Goatface silicon	Planned Phase 5

Phase 4 — FPGA Prototype¶

Status: ⚪ Future

Prototype NCI-1 hardware primitives on a Xilinx Artix-7 FPGA. Reprogrammable silicon — design, flash, test, iterate without a fab. This is the bridge between software and custom chip.

Target hardware: Digilent Arty A7 (Artix-7)
Toolchain: Xilinx Vivado + CIRCT
Compression engine in hardware
Tensor multiply unit
Graph traversal unit
Ethics Core prototype — immutable rule enforcement in silicon
Terse → CIRCT → Verilog compiler target

Phase 5 — NCI-1 Custom Chip¶

Status: ⚪ Future

Tape out the NCI-1 chip based on validated FPGA design. Purpose-built AI silicon with Terse primitives in hardware. The language and the chip designed together from day one.

FPGA design validated and stable
RTL design finalized
Foundry selection — TSMC, GlobalFoundries, or RISC-V open fab
NCI-1 tape out
NCI Box appliance — first product shipping NCI-1
Terse self-hosting — Terse compiler written in Terse

Phase 6 — NCI Ethics Core Chip¶

Status: ⚪ Future

A dedicated hardware ethics enforcement chip. Sits physically between any AI system and the outside world. Ethics rules written in Terse, executed in silicon.

The Principle

"You can't jailbreak silicon. A hardware ethics engine is not a filter — it is a physical constraint. No software layer can override it because it is upstream of all software."

Ethics rule engine in Verilog — from FPGA prototype
Immutable rule storage — one-time programmable memory
Tamper-evident audit log in hardware
PCIe Ethics Card — plugs into any server
Ethics IP Block — licensable silicon for third-party chips
Integrated on all NCI Box appliances

The Vertical Stack¶

Three original works. One coherent vision.

NCI Ethics Core Chip
        ↑
    NCI-1 Chip  ←  Terse compiler targets this silicon
        ↑
      Terse       ←  Language primitives match the hardware
        ↑
      NCI         ←  Terse is NCI's native language

No other organization currently holds this combination of language, compiler, and dedicated ethics silicon.

Authored by Lesley Ancion · Goatface Tech · Sundre, Alberta · 2026